Technical Field
The disclosure relates to computing by means of digital devices.
One or more embodiments may related to performing mathematical operations such as division or multiplication, e.g., in Integrated Circuit (IC) products.
Description of the Related Art
IC products increasingly embed digital hardware components for implementing specific control or DSP functions. The chip (e.g., silicon) area hosting these dedicated hardware components may be one of the factors affecting the cost of the product.
Control or Digital Signal Processor (DSP) functions may involve, e.g., divider blocks. As a consequence, reducing the cost of dividers may be a key for achieving competitive designs.
Digital circuits aimed at performing division may be costly, and cost may be a key differentiation aspect when designing a related Application Specific Integrated Circuit or ASIC.
The literature describes various different approaches to implement arithmetic division, mostly devised to be applied for CPUs, e.g., with the aim of implementing high performance floating point division, possibly by resorting to rather complex numerical techniques.
When targeting low-cost division of integer numbers, a sequential approach may be an option, in which case the cost may be reduced with a possible negative effect on performance. Exemplary of simple and well known sequential approaches to division are “Repeated Subtraction” and “Non-restoring” parallel division.
In repeated subtraction the divisor (or denominator) M may be sequentially subtracted from the dividend (or numerator) D and the quotient Q=D/M is identified by the number of times subtraction may take place before reaching a negative value. Each step of this algorithm consumes one clock cycle. As a consequence, achieving the division product, that is the quotient Q, may involve Q clock cycles. This may be too high a figure for many applications to achieve a reasonable speed. Also, a multi-cycle may not always be feasible as this may involve a fast extra clock, and such a fast clock (Q times faster) may lead to extra cost and extra power.
Combinatorial “non-restoring” divider implementations are disclosed. A problem with this approach is the intrinsic complexity of the implementation and the related cost.
It will be otherwise appreciated that the discussion above and related to division may apply also to multiplication (division being in fact a multiplication where the multiplier has a negative exponent). For instance, multiplication may be implemented as repeated addition (sum) where the multiplicand is sequentially summed or added a number of times identified by the multiplier.